To maintain product quality, manufacturers of semiconductor devices perform tests on their products prior to shipment to consumers. During testing, one or more devices-under-test (DUTs) are stimulated by signals from automatic test equipment (ATE) which is configured to receive and analyze the responses from the DUTs. As an example, DUTs can include dies on a wafer or integrated circuit (IC) chips. Testing for a given set of DUTs is typically performed in parallel, such that a given test is performed concurrently from start to finish for each DUT in the given set. As a result, a large number of DUTs can be tested in a relatively short amount of time.
To perform tests on a given set of DUTs, a DUT test system provides operating power to the DUTs. The DUTs are thus able to perform their test functions using the operating power that is supplied to them. Accordingly, a power supply on the DUT test system is sized according to the current requirements of the DUTs for which the DUT test system is conducting the test functions. However, during a given test, or from one test to another, the power requirements of a given DUT often changes. For example, a given test can have multiple stages, with some of the stages requiring greater amounts of current than others. As a result, the power supply of the DUT test system can typically be sized according to the worst case scenario of the current draw of the tests. Therefore, for less current intensive tests or test stages, power supply capacity can be largely unused, resulting in an inefficiency of the test process.